uPSD34xx

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Table 1. Device Summary

Note: Operating temperature is in the Industrial range (–40°C to 85°C).

SUMMARY DESCRIPTION

The

powerful 8051-based microcontroller with a flexi-

ble memory structure, programmable logic, and a

rich peripheral mix to form an ideal embedded

controller. At its core is a fast 4-cycle 8032 MCU

with a 4-byte instruction prefetch queue (PFQ) and

a 4-entry fully associative branching cache (BC).

The MCU is connected to a 16-bit internal instruc-

tion path to maximize performance, enabling loops

of code in smaller localities to execute extremely

fast. The 16-bit wide instruction path in the

Turbo

fetched from memory in a single memory cycle.

This keeps the average performance near its peak

performance (peak performance for 5V, 40MHz

Turbo

instructions, and average performance will be ap-

proximately 9 MIPS for mix of single- and multi-

byte instructions).

USB 2.0 (full speed, 12Mbps) is included, provid-

ing 10 endpoints, each with its own 64-byte FIFO

to maintain high data throughput. Endpoint 0 (Con-

trol Endpoint) uses two of the 10 endpoints for In

and Out directions, the remaining eight endpoints

may be allocated in any mix to either type of trans-

fers: Bulk or Interrupt.

Code development is easily managed without a

hardware In-Circuit Emulator by using the serial

JTAG debug interface. JTAG is also used for In-

System Programming (ISP) in as little as 10 sec-

onds, perfect for manufacturing and lab develop-

ment. The 8032 core is coupled to Programmable

System Device (PSD) architecture to optimize the

8032 memory structure, offering two independent

banks of Flash memory that can be placed at vir-

tually any address within 8032 program or data ad-

dress space, and easily paged beyond 64K bytes

using on-chip programmable decode logic.

Dual Flash memory banks provide a robust solu-

tion for remote product updates in the field through

In-Application Programming (IAP). Dual Flash

banks also support EEPROM emulation, eliminat-

ing the need for external EEPROM chips.

General purpose programmable logic (PLD) is in-

cluded to build an endless variety of glue-logic,

saving external logic devices. The PLD is config-

ured using the software development tool, PSD-

soft

Express,

available

from

the

web

at

www.st.com/psm, at no charge.

The uPSD34xx also includes supervisor functions

such as a programmable watchdog timer and low-

voltage reset.

Part Number

Max MHz

1st

Flash

(bytes)

2nd

Flash

SRAM

GPIO

8032

Bus

Pkg.

uPSD3422E-40T6

40

64K

32K

4K

35

No

3.3V

5.0V

TQFP52

uPSD3422EV-40T6

40

64K

32K

4K

35

No

3.3V

3.3V

TQFP52

uPSD3422E-40U6

40

64K

32K

4K

46

Yes

3.3V

5.0V

TQFP80

uPSD3422EV-40U6

40

64K

32K

4K

46

Yes

3.3V

3.3V

TQFP80

uPSD3433E-40T6

40

128K

32K

8K

35

No

3.3V

5.0V

TQFP52

uPSD3433EV-40T6

40

128K

32K

8K

35

No

3.3V

3.3V

TQFP52

uPSD3433E-40U6

40

128K

32K

8K

46

Yes

3.3V

5.0V

TQFP80

uPSD3433EV-40U6

40

128K

32K

8K

46

Yes

3.3V

3.3V

TQFP80

uPSD3434E-40T6

40

256K

32K

8K

35

No

3.3V

5.0V

TQFP52

uPSD3434EV-40T6

40

256K

32K

8K

35

No

3.3V

3.3V

TQFP52

uPSD3434E-40U6

40

256K

32K

8K

46

Yes

3.3V

5.0V

TQFP80

uPSD3434EV-40U6

40

256K

32K

8K

46

Yes

3.3V

3.3V

TQFP80