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AD1934YSTZ Datasheet(PDF) 7 Page - Analog Devices |
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AD1934YSTZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 28 page AD1934 Rev. 0 | Page 7 of 28 Parameter Condition Comments Min Max Unit DAC SERIAL PORT See Figure 16 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns AUXTDM SERIAL PORT See Figure 17 tABH AUXTDMBCLK high Slave mode 10 ns tABL AUXTDMBCLK low Slave mode 10 ns tALS AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns tALH AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns tALS AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns tDDH DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns AUXILIARY INTERFACE tDXDD AUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns |
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