internal clock

In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and

conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after

each conversion.

OR

Auto Power Down

CS

WR

CSTART

INTCLK

RD

D[0:9]

INT

EOC

Config

Data

ADC

Data

ADC

Data

t su(CSL_WRL)

t h(WRH_CSH)

t

d(CSH_CSTARTL)

(Channel 0)

(see Note A)

t su(DAV_WRH)

th(WRH_DAV)

t su(CSL_RDL)

th(RDH_CSH)

t en(RDL_DAV)

t dis(RDH_DAV)

t su(CSL_RDL)

t en(RDL_DAV)

t (STARTOSC)

t (STARTOSC)

9

10

1

0

Auto Power Down

(Channel 1)

(see Note A)

t d(EOC_RDL)

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 5. Multichannel Input Mode Conversion – Hardware CSTART, Internal Clock