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PLDC20RA10-20WMB Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # PLDC20RA10-20WMB
Description  Reprogrammable Asynchronous CMOS Logic Device
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

PLDC20RA10-20WMB Datasheet(HTML) 7 Page - Cypress Semiconductor

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PLDC20RA10
Document #: 38-03012 Rev. **
Page 7 of 14
Switching Characteristics Over the Operating Range[3, 7, 8]
Parameter
Description
Commercial
Military
Unit
–15
–20
–20
–25
–35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tPD
Input or Feedback to
Non-Registered Output
15
20
20
25
35
ns
tEA
Input to Output Enable
15
20
20
30
35
ns
tER
Input to Output
Disable
15
20
20
30
35
ns
tPZX
Pin 13 to Output
Enable
12
15
15
20
25
ns
tPXZ
Pin 13 to Output
Disable
12
15
15
20
25
ns
tCO
Clock to Output
15
20
20
25
35
ns
tSU
Input or Feedback
Set-Up Time
7
10
10
15
20
ns
tH
Hold Time
3
5
3
5
5
ns
tP
Clock Period
(tSU + tCO)
22
30
30
40
55
ns
tWH
Clock Width HIGH[5]
10
13
12
18
25
ns
tWL
Clock Width LOW[5]
10
13
12
18
25
ns
fMAX
Maximum Frequency
(1/tP)
[5]
45.5
33.3
33.3
25.0
18.1
MHz
tS
Input of Asynchronous
Set to Registered Output
15
20
20
25
40
ns
tR
Input of Asynchronous
Reset to Registered
Output
15
20
20
25
40
ns
tARW
Asynchronous Reset
Width[5]
15
20
20
25
25
ns
tASW
Asynchronous S-Width[5]
15
20
20
25
25
ns
tAR
Asynchronous Set/
Reset Recovery Time
10
12
12
15
20
ns
tWP
Preload Pulse Width
15
15
15
15
15
ns
tSUP
Preload Set-Up Time
15
15
15
15
15
ns
tHP
Preload Hold Time
15
15
15
15
15
ns
Notes:
7.
Part (a) of AC Test Loads was used for all parameters except tEA, tER, tPZX and tPXZ, which use part (b).
8.
The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.


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