LX8117-xx/8117A-xx/8117B-xx

PRODUCT DA T ABOOK 1996/1997

Copyright © 1999

Rev. 1.5a

2

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Power Dissipation .................................................................................. Internally Limited

Input Voltage

LX8117-00/8117A-00/8117B-00 (Adj.) ..................................................................... 15V

LX8117-33/8117A-33/8117B-33 (3.3V), LX8117-05/8117A-05/8117B-05 (5.0V) .... 15V

LX8117-25/8117A-25/8117B-25 (2.5V), LX8117-28/8117A-28/8117B-28 (2.85V) .. 12V

Surge Voltage ............................................................................................................... 15V

Operating Junction Temperature

Plastic (ST, DD & DT Packages) .......................................................................... 150°C

Storage Temperature Range ...................................................................... -65°C to 150°C

Lead Temperature (Soldering, 10 seconds) ............................................................. 300°C

Short-Circuit Protection ....................................................................................... Indefinite

Note 1. Exceeding these ratings could cause damage to the device. All voltages are with

respect to Ground. Currents are positive into, negative out of the specified terminal.

PACKAGE PIN OUTS

3. IN

2. OUT

1. ADJ / GND

ST PACKAGE

(Top View)

3

2

1

(Top View)

THERMAL DATA

TAB IS V

OUT

ST PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JT

15°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

*150°C/W

DD PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JT

10°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

*60°C/W

DT PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JC

9°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

*80°C/W

Junction Temperature Calculation: T

J

= T

A

+ (P

D

x

θ

JA

). The

θ

JA

numbers are guidelines for the

thermal performance of the device/pc-board system. All of the above assume no ambient airflow.

*

θ

plane or internal power plane.

θ

mounting technique. (See Application Notes Section: Thermal Considerations)

TAB IS V

OUT

BLOCK DIAGRAM

Thermal

Limit Circuit

Control

Circuit

Bandgap

Circuit

Output

Circuit

Bias

Circuit

V

OUT

V

IN

Current

Limit Circuit

ADJ

3. IN

2. OUT

1. ADJ / GND

DT PACKAGE (D-Pak)

(Top View)

TAB IS V

OUT

IN

OUT

ADJ / GND

RoHS Peak Package Solder Reflow Temp. (40 seconds max. exposure)............................ 260°C (+0, -5)

RoHS / Pb-free 100% Matte Tin Lead Finish