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M28W640HCB70N6E Datasheet(PDF) 7 Page - Numonyx B.V |
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M28W640HCB70N6E Datasheet(HTML) 7 Page - Numonyx B.V |
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7 / 72 page  M28W640HCT, M28W640HCB Description 7/72 1 Description The M28W640HCT and M28W640HCB are 64 Mbit (4 Mbit x 16) non-volatile Flash memories that can be erased electrically at block level and programmed in-system on a word-by-word basis using a 2.7 V to 3.6 V VDD supply. An optional 12V VPP power supply is provided to speed up customer programming. The devices feature an asymmetrical blocked architecture. They have an array of 135 blocks: 8 parameter blocks of 4 Kwords and 127 main blocks of 32 Kwords. The M28W640HCT has the parameter blocks at the top of the memory address space while the M28W640HCB locates the parameter blocks starting from the bottom. The memory maps are shown in Figure 4: Block addresses. The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked- down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 192-bit protection register to increase the protection of a system design. The protection register is divided into a 64-bit segment and a 128-bit segment. The 64-bit segment contains a unique device number written by Numonyx, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 5, shows the protection register memory map. Program and Erase commands are written to the command interface of the memory. An on- chip Program/Erase controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (12 × 20 mm) and TFBGA48 (6.39 × 10.5 mm, 0.75 mm pitch) packages and is supplied with all the bits erased (set to ’1’). |
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