Signal descriptions

M36L0R7060T1, M36L0R7060B1

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2.5

Wait (WAIT)

WAIT is an output pin common to the Flash memory and PSRAM components. However the

WAIT signal does not behave in the same way for the PSRAM and the Flash memory.

For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM

and to the M58LR128HTB datasheet for the Flash memory.

2.6

The Flash Chip Enable input activates the control logic, input buffers, decoders and sense

deselected, the outputs are high impedance and the power consumption is reduced to the

standby level.

2.7

The Output Enable pin controls the data outputs during Flash memory Bus Read

operations.

2.8

The Write Enable controls the Bus Write operation of the Flash memory’s Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.9

Write Protect is an input that gives an additional hardware protection for each block. When

and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the

M30L0R7000T1/B1 datasheet).

2.10

memory is in Reset mode: the outputs are high impedance and the current consumption is

device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied