1.8V, Dual, 12-Bit, 210Msps ADC for

Broadband Applications

4

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DC ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CHANNEL CROSSTALK AND CHANNEL MATCHING SPECIFICATIONS

Channel Isolation

90

dB

LVCMOS LOGIC INPUTS (CLKDIV,

T/BA, T/BB)

Input High Voltage

0.8 x

V

Input Low Voltage

0.2 x

V

Input Capacitance

2pF

LVDS DIGITAL OUTPUTS (DA0P/N–DA11P/N, DB0P/N–DB11P/N, ORAP/N, ORBP/N, DCOP/N)

Differential Output Voltage

225

490

mV

Output Offset Voltage

1.125

1.310

V

OUTPUT TIMING CHARACTERISTICS

CLK to Data Propagation Delay

Figure 5 (Note 3)

1.7

ns

CLK to DCO Propagation Delay

Figure 5 (Note 3)

3.7

ns

DCO to Data Propagation Delay

2.3

2.7

3.1

ns

LVDS Output Rise Time

350

ns

LVDS Output Fall Time

350

ns

Output Data Pipeline Delay

Figure 5

11

Clock

Cycles

POWER REQUIREMENTS

Analog Supply Voltage Range

1.71

1.8

1.89

V

Output Supply Voltage Range

1.71

1.8

1.89

V

Analog Supply Current

760

900

mA

Output Supply Current

120

160

mA

Analog Power Dissipation

1.6

1.908

W

Power-Supply Rejection Ratio

PSRR

5

mV/V

characterization.

Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points.

The full-scale range (FSR) is defined as 4095 x slope of the line.

Note 4: ENOB and SINAD are computed from a curve fit.

Note 5: PSRR is measured with the analog and output supplies connected to the same potential.