Si9976

Vishay Siliconix

Document Number: 70016

S-40757—Rev. F, 19-Apr-04

www.vishay.com

3

SPECIFICATIONSa

Limits

D Suffix −40 to 85_C

Test Conditions

UnlessOtherwise Specified

Parameter

Unit

Maxc

Typb

Minc

V+ = 20 to 40 V

Symbol

Dynamic

Propogation Delay Time

t

G1

350

Propogation Delay Time

Low to High Level

G2

400

Propogation Delay Time

G1

150

Propogation Delay Time

High to Low Level

G2

50

Propogation Delay Time, Low to High Lev-

el, Enable-to-Fault Output

50% IN to FAULT = 2 V, S1 shorted to GND or V+

500

ns

Output Rise Time (G1, G2)

110

Output Fall Time (G1, G2)

50

Short Circuit Pulse Width

350

Notes

a.

Refer to PROCESS OPTION FLOWCHART for additional information.

b.

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

c.

The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.

d.

To supply the output current of 10 mA on a dc basis, an external 13-V supply must be connected between the CAP pin and the S1 pin with the negative terminal

respect to V+.

e.

f.

Internally generated voltage for reference only.

g.

TRUTH TABLE

EN

IN

Condition

FAULT OUTPUT

G1 OUT

G2 OUT

1

0

Normal Operation

0

Low

High

1

1

Normal Operation

0

High

Low

0

X

Disabled

Low

Low

1

0

Load Shorted to V+

Low

Low

1

1

Load Shorted to Ground

Low

Low

1

1

0

Low

Low

1

0

0

Low

High

X

X

1

Low

Low

Notes

a.

FAULT output retains previous state until ENABLE rising edge.

b.

Latch FAULT condition, reset by ENABLE rising edge.

c.