M58PR001LE96ZAD5 datasheet(4/123 Pages) NUMONYX

Part #	M58PR001LE96ZAD5

Description	512-Mbit or 1-Gbit (횞 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories

Download	123 Pages

Scroll/Zoom	100%

Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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4 / 123 page

Contents

M58PR512LE, M58PR001LE

4/123

5.3.1

Single word program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3.2

Buffer program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3.3

Buffer enhanced factory program method . . . . . . . . . . . . . . . . . . . . . . . 47

6

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1

Control program mode status bit (SR9) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2

Object program mode status bit (SR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.3

Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 49

6.4

Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.5

Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.6

Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.7

VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.8

Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.9

Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.10

Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 51

7

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.1

Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2

X latency bits (CR14-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.3

Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.4

Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.5

Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8

Enhanced configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.1

Deep power-down mode bit (ECR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2

Deep power-down polarity bit (ECR14) . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3

Output driver control bits (ECR2-ECR0) . . . . . . . . . . . . . . . . . . . . . . . . . 58

9

Extended flash array (EFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.1

Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2

Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.3

Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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