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MM2201VB1TR Datasheet(PDF) 9 Page - STMicroelectronics |
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MM2201VB1TR Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 15 page ACK NO ACK BYTE WRITE R/W = 0 BYTE ADDR DATA IN WC PAGE WRITE BYTE ADDR DATA IN 1 WC AI01324 DATA IN 4 R/W = 0 ACK NO ACK NO ACK NO ACK Figure 8. Write Modes Sequences with Write Control = 1 (M2201 and M2201V) Read Operation Byte Read. The master sends a START condition followed by seven bits of address and the RW bit (set to ’1’). The M2201 acknowledges it and outputs the corresponding data byte. The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). Sequential Read. The master sends a START condition followed by seven bits of address and the RW bit (set to ’1’). The M2201 acknowledges it and outputs the corresponding data byte. The master does acknowledge this byte and reads the next data byte (at address + 1). The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will ’roll- over to address ’00’ and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the M2201 waits for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the M2201 terminates the data transfer and switches to a standby state. 9/15 M2201 |
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