M58WR064KU datasheet(4/123 Pages) NUMONYX

Part #	M58WR064KU

Description	16-, 32- and 64-Mbit (x 16, Mux I/O, Multiple Bank, Burst) 1.8 V supply Flash memories

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Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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4 / 123 page

Contents

M58WRxxxKU, M58WRxxxKL

4/123

7.7

Block Protection Status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.8

Bank Write/Multiple Word Program Status bit (SR0) . . . . . . . . . . . . . . . . 40

8

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.1

Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.2

Bus Invert Configuration (CR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.3

X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4

Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.5

Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6

Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.7

Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.8

Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.9

Power-Down bit (CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.10

Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.11

Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1

Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.2

Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.2.1

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.3

Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10

Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 54

11

Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.1

Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.2

Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.3

Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.4

Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.5

Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 57

12

Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 59

13

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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