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ISPLSI1016EA-125LJ44 Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPLSI1016EA-125LJ44 Datasheet(HTML) 2 Page - Lattice Semiconductor |
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2 / 13 page  2 Specifications ispLSI 1016EA Functional Block Diagram Figure 1. ispLSI 1016EA Functional Block Diagram The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 2 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. By connecting the VCCIO pin to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V-compatible voltages. Eight GLBs, 16 I/O cells, a dedicated input (if available) and one ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1016EA device contains two Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1016EA device are selected using the Clock Distribution Network. Two dedicated clock pins (Y0 and Y1) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016EA device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 1016EA are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. I/O 0 I/O 1 I/O 2 I/O 3 GOE 0 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 TDI TDO TMS TCK I/O 4 I/O 5 VCCIO Global Routing Pool (GRP) CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Clock Distribution Network A0 A1 A2 A3 A4 A5 A6 A7 B7 B6 B5 B4 B3 B2 B1 B0 Generic Logic Blocks (GLBs) Megablock *Note: Y1 and RESET are multiplexed on the same pin 0139/1016EA |
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