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MM24256-ARMN6T Datasheet(PDF) 1 Page - STMicroelectronics |
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MM24256-ARMN6T Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 20 page 1/20 NOT FOR NEW DESIGN November 2001 This is information on a product still in production but not recommended for new designs. M24256-A 256 Kbit Serial I²C Bus EEPROM With Two Chip Enable Lines This device is now designated as “Not for New De- sign”. Please use the M24256-B in all future de- signs (as described in application note AN1470). s Compatible with I2C Extended Addressing s Two Wire I2C Serial Interface Supports 400 kHz Protocol s Single Supply Voltage: – 4.5V to 5.5V for M24256-A – 2.5V to 5.5V for M24256-AW s 2 Chip Enable Inputs: up to four memories can be connected to the same I2C bus s Hardware Write Control s BYTE and PAGE WRITE (up to 64 Bytes) s RANDOM and SEQUENTIAL READ Modes s Self-Timed Programming Cycle s Automatic Address Incrementing s Enhanced ESD/Latch-Up Behavior s More than 100,000 Erase/Write Cycles s More than 40 Year Data Retention DESCRIPTION These I2C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32Kx8 bits, and operate down to 2.5 V (for the M24256-AW). The M24256-A is available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Out- Figure 1. Logic Diagram AI02271C SDA VCC M24256-A WC SCL VSS 2 E0-E1 Table 1. Signal Names E0, E1 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground PDIP8 (BN) 0.25 mm frame SO8 (MN) 150 mil width TSSOP14 (DL) 169 mil width 8 1 8 1 SO8 (MW) 200 mil width 8 1 SBGA SBGA7 (EA) 140 x 90 mil |
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