2

PS8924A

11/29/07

PI3HDMI101

HDMI, High-Definition Multimedia Interface, and Deep Color are trademarks of

HDMI Licensing, LLC in the United States and other countries.

ADVANCE INFORMATION - COMPANY CONFIDENTIAL

Pin Configuration

TMDS Receiver Block

CLK+/-

250Kohm

R

AV

1

DD

Control

Rx Sense

Each high speed data and clock input has integrated equalization that can eliminate deterministic jitter caused

by input cables. All activity can be configured using pin strapping. The Rx block is designed to receive all rel-

pixel clock, and DDC signals. Pixel clock channel has following temination scheme for Rx Sense support.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

42 41 40 39

18 19 20 21

SCL_T

VDD

GND

OUT_CLK–

OUT_CLK+

VDD

OUT_D0–

OUT_D0+

GND

OUT_D1–

OUT_D1+

VDD

OUT_D2–

OUT_D2+

GND

VDD

OC_S3

EQ_S0

EQ_S1

GND

IN_CLK–

IN_CLK+

VDD

IN_D0–

IN_D0+

GND

IN_D1–

IN_D1+

VDD

IN_D2–

IN_D2+

GND

Rx_Sense

DCC_EN

GND

Rx Sense

termination is 250k

Ω

termination is 50

Ω

07-0230