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MM24128-BWMN6T Datasheet(PDF) 3 Page - STMicroelectronics |
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MM24128-BWMN6T Datasheet(HTML) 3 Page - STMicroelectronics |
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3 / 17 page  3/17 M24256, M24128 er clock, the master must have an open drain out- put, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to trans- fer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowl- edged. Please see the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communica- tion. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device con- tinuously monitors (except during a programming cycle) the SDA and SCL lines for a START condi- tion, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communica- tion between the memory device and the bus mas- ter. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a suc- cessful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I 2C Bus AI01665 VCC CBUS SDA RL MASTER RL SCL CBUS 100 0 4 8 12 16 20 CBUS (pF) 10 1000 fc = 400kHz fc = 100kHz |
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