M25P05 datasheet(5/32 Pages) STMICROELECTRONICS

Part #	M25P05

Description	512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M25P05

OPERATING FEATURES

Page Programming

To program one data byte, two instructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP)

instruction allows up to 128 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memory need to have been erased to all

1s (FFh). This can be achieved either a sector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status

Register (WRSR), Program (PP) or Erase (SE or

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provided in the Status Regis-

ter so that the application program can monitor its

value, polling it to establish when the previous

Write cycle, Program cycle or Erase cycle is com-

plete.

Active Power, Stand-by Power and Deep

Power-Down Modes

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode.

When Chip Select (S) is High, the device is dis-

abled, but could remain in the Active Power mode

until all internal cycles have completed (Program,

Erase, Write Status Register). The device then

goes in to the Stand-by Power mode. The device

consumption drops to ICC1.

The Deep Power-down mode is entered when the

specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device

consumption drops further to ICC2. The device re-

mains in this mode until another specific instruc-

tion (the Release from Deep Power-down Mode

and Read Electronic Signature (RES) instruction)

is executed.

All other instructions are ignored while the device

is in the Deep Power-down mode. This can be

used as an extra software protection mechanism,

when the device is not in active use, to protect the

device from inadvertant Write, Program or Erase

instructions.

Status Register

The Status Register contains a number of status

and control bits, as shown in Table 5, that can be

read or set (as appropriate) by specific instruc-

tions.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

Register, Program or Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP1, BP0) become

read-only bits.

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