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MM24512-WBN5T Datasheet(PDF) 10 Page - STMicroelectronics

Part # MM24512-WBN5T
Description  512 Kbit Serial I짰 Bus EEPROM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MM24512-WBN5T Datasheet(HTML) 10 Page - STMicroelectronics

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M24512
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Figure 8. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table
14., but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
The sequence, as shown in Figure 8., is:
–
Initial condition: a Write cycle is in progress.
–
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
–
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES
NO
START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation


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