MM24256-BBN6T datasheet(5/17 Pages) STMICROELECTRONICS

Part #	MM24256-BBN6T

Description	256/128 Kbit Serial I짼C Bus EEPROM Without Chip Enable Lines

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M24256, M24128

There are two modes both for read and write.

These are summarized in Table 4 and described

later. A communication between the master and

the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two

byte wide) address. The Most Significant Byte (Ta-

ble 5) is sent first, followed by the Least significant

Byte (Table 6). Bits b15 to b0 form the address of

the byte in memory. Bit b15 is treated as a Don’t

Care bit on the M24256 memory. Bits b15 and b14

are treated as Don’t Care bits on the M24128

memory.

Table 4. Operating Modes

Note: 1. X =

VIH or VIL.

Mode

RW bit

WC 1

Data Bytes

Initial Sequence

Current Address Read

1

X

1

START, Device Select, RW = ‘1’

Random Address Read

0X

1

START, Device Select, RW = ‘0’, Address

1

X

reSTART, Device Select, RW = ‘1’

Sequential Read

1

X

≥ 1

Similar to Current or Random Address Read

Byte Write

0

VIL

1

START, Device Select, RW = ‘0’

Page Write

0

VIL

≤ 64

START, Device Select, RW = ‘0’

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01120C

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

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MM24256-BBN6T Datasheet(PDF) 5 Page - STMicroelectronics

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