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OMAP3503 Datasheet(PDF) 1 Page - Texas Instruments |
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OMAP3503 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 227 page  www.ti.com 1 OMAP3515/03 Applications Processor 1.1 Features OMAP3515/03 Applications Processor SPRS505 – FEBRUARY 2008 • External Memory Interfaces: • OMAP3515/03 Applications Processor: – SDRAM Controller (SDRC) – OMAP™ 3 Architecture • 16, 32-bit Memory Controller With – MPU Subsystem 2G-Byte Total Address Space • 600-MHz ARM Cortex™-A8 Core • Interfaces to Low-Power Double Data • NEON™ SIMD Coprocessor Rate (LPDDR) SDRAM – 2D/3D Graphics Accelerator (OMAP3515 • SDRAM Memory Scheduler (SMS) and Device Only) Rotation Engine • Tile Based Architecture Delivering 10 – General Purpose Memory Controller MPoly/sec (GPMC) • Universal Scalable Shader Engine: • 16-bit Wide Multiplexed Address/Data Multi-threaded Engine Incorporating Bus Pixel and Vertex Shader Functionality • Up to 8 Chip Select Pins With 129M-Byte • Industry Standard API Support: Address Space per Chip Select Pin OpenGLES 1.1 and 2.0, OpenVG1.0 and • Glueless Interface to NOR Flash, NAND Direct3D Mobile Flash (With ECC Hamming Code • Fine Grained Task Switching, Load Calculation), SRAM and Pseudo-SRAM Balancing, and Power Management • Flexible Asynchronous Protocol Control • Programmable High Quality Image for Interface to Custom Logic (FPGA, Anti-Aliasing CPLD, ASICs, etc.) – Fully Software-Compatible With ARM9™ • Nonmultiplexed Address/Data Mode • ARM Cortex™-A8 Core (Limited 2K-Byte Address Space) – ARMv7 Architecture • System Direct Memory Access (sDMA) • Trust Zone® Controller (32 Logical Channels With • Thumb®-2 Configurable Priority) • MMU Enhancements • Camera Image Signal Processing (ISP) – In-Order, Dual-Issue, Superscalar – CCD and CMOS Imager Interface Microprocessor Core – Memory Data Input – NEON™ Multimedia Architecture – RAW Data Interface – Over 2x Performance of ARMv6 SIMD – BT.601/BT.656 Digital YCbCr 4:2:2 – Supports Both Integer and Floating Point (8-/16-Bit) Interface SIMD – A-Law Compression and Decompression – Jazelle® RCT Execution Environment – Preview Engine for Real-Time Image Architecture Processing – Dynamic Branch Prediction with Branch – Glueless Interface to Common Video Target Address Cache, Global History Decoders Buffer, and 8-Entry Return Stack – Histogram Module/Auto-Exposure, – Embedded Trace Macrocell (ETM) Support Auto-White Balance, and Auto-Focus for Non-Invasive Debug Engine • ARM Cortex™-A8 Memory Architecture: – Resize Engine – 16K-Byte Instruction Cache (4-Way • Resize Images From 1/4x to 4x Set-Associative) • Separate Horizontal/Vertical Control – 16K-Byte Data Cache (4-Way • Display Subsystem Set-Associative) – Parallel Digital Output – 256K-Byte L2 Cache • Up to 24-Bit RGB • Endianess: ARM Big Endian • HD Maximum Resolution Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. is a trademark of ~ Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the Copyright © 2008, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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