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PI2EQX4402D Datasheet(PDF) 3 Page - Pericom Semiconductor Corporation |
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PI2EQX4402D Datasheet(HTML) 3 Page - Pericom Semiconductor Corporation |
3 / 8 page 3 PS8873B 11/16/06 PI2EQX4402D 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer with Signal Detect feature Pin Description Pin # Pin Name I/O Description B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 VDD PWR 1.8V Supply Voltage C3 AI+ I Positive CML Input Channel A with internal 50Ω pull down during normal operation (EN_A=1). When EN_A=0, this pin is high impedance. D3 AI- I Negative CML Input Channel A with internal 50Ω pull down during normal operation (EN_A=1). When EN_A=0, this pin is high impedance. E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 GND PWR Supply Ground C8 BI+ I Positive CML Input Channel B with internal 50Ω pull down during normal operation (EN_B=1). When EN_B=0, this pin is high impedance. D8 BI- I Negative CML Input Channel B with internal 50Ω pull down during normal operation (EN_B=1). When EN_B=0, this pin is high impedance. G3 CI+ I Positive CML Input Channel C with internal 50Ω pull down during normal operation (EN_C=1). When EN_C=0, this pin is high impedance. H3 CI- I Negative CML Input Channel C with internal 50Ω pull down during normal operation (EN_C=1). When EN_C=0, this pin is high impedance. G8 DI+ I Positive CML Input Channel D with internal 50Ω pull down during normal operation (EN_D=1). When EN_D=0, this pin is high impedance. H8 DI- I Negative CML Input Channel D with internal 50Ω pull down during normal operation (EN_D=1). When EN_D=0, this pin is high impedance. A3, B4, B5 SEL[0: 2]_A I Selection pins for equalizer (see Amplifier Configuration Table) w/ 50KΩ internal pull up A4, C4, C5 SEL[0:2]_B I G2, J2, J4 SEL[0:2]_C I H2, K2, J5 SEL[0:2]_D I B6, A5 SEL[3:4]_A I Selection pins for amplifier (see Amplifier Configuration Table) w/ 50KΩ internal pull up C6, A6 SEL[3:4]_B I K3, K4 SEL[3:4]_C I J6, J9 SEL[3:4]_D I B7, A7 SEL[5:6]_A I Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50KΩ internal pull up C7, A8 SEL[5:6]_B I K9, G9 SEL[5:6]_C I K10, H9 SEL[5:6]_D I C10 AO+ O Positive CML Output Channel A internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. D10 AO- O Negative CML Output Channel A with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. C1 BO+ O Positive CML Output Channel B with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. D1 BO- O Negative CMLOutput Channel B with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. G10 CO+ O Positive CMLOutput Channel C with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. H10 CO- O Negative CMLOutput Channel C with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. 06-0306 |
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