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M24C64DW6T Datasheet(PDF) 10 Page - STMicroelectronics

Part # M24C64DW6T
Description  64/32 Kbit Serial I짼C Bus EEPROM
Download  19 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C64DW6T Datasheet(HTML) 10 Page - STMicroelectronics

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M24C64, M24C32
10/26
Page Write
The Page Write mode allows up to 32 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b12-b5 for M24C64, and b11-b5 for M24C32) are
the same. If more bytes are sent than will fit up to
the end of the row, a condition known as ‘roll-over’
occurs. This should be avoided, as data starts to
become overwritten in an implementation depen-
dent way.
The bus master sends from 1 to 32 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 5 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01106C
PAGE WRITE
(cont'd)
WC (cont'd)
DATA IN N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK


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