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82801CA Datasheet(PDF) 6 Page - Intel Corporation

Part # 82801CA
Description  I/O Controller Hub 3-S (ICH3-S)
Download  521 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82801CA Datasheet(HTML) 6 Page - Intel Corporation

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Intel® 82801CA ICH3-S
Datasheet
5.1.6.1
Type 0 to Type 0 Forwarding ............................................ 69
5.1.6.2
Type 1 to Type 0 Conversion ............................................ 69
5.1.7
PCI Dual Address Cycle (DAC) Support........................................... 70
5.2
LAN Controller (B1:D8:F0)............................................................................. 71
5.2.1
Feature Summary ............................................................................. 71
5.2.2
LAN Controller Architectural Overview ............................................. 72
5.2.2.1
Parallel Subsystem............................................................ 72
5.2.2.2
FIFO Subsystem ............................................................... 73
5.2.2.3
Serial CSMA/CD Unit ........................................................ 73
5.2.3
LAN Controller PCI Bus Interface ..................................................... 74
5.2.3.1
Bus Slave Operation ......................................................... 74
5.2.3.2
Bus Master Operation ....................................................... 75
5.2.3.3
PCI Power Management ................................................... 78
5.2.3.4
PCI Reset Signal ............................................................... 80
5.2.3.5
Wake-Up Events ............................................................... 80
5.2.3.6
Wake on LAN* (Preboot Wake-Up)................................... 81
5.2.4
Serial EEPROM Interface ................................................................. 82
5.2.5
CSMA/CD Unit .................................................................................. 82
5.2.5.1
Full Duplex ........................................................................ 83
5.2.5.2
Flow Control ...................................................................... 83
5.2.5.3
Address Filtering Modifications ......................................... 83
5.2.5.4
VLAN Support ................................................................... 83
5.2.6
Media Management Interface ........................................................... 84
5.2.7
TCO Functionality ............................................................................. 84
5.2.7.1
Receive Functionality ........................................................ 84
5.2.7.2
Transmit Functionality ....................................................... 84
5.3
LPC Bridge (w/ System and Management Functions) (D31:F0).................... 85
5.3.1
LPC Interface .................................................................................... 85
5.3.1.1
LPC Cycle Types............................................................... 86
5.3.1.2
Start Field Definition .......................................................... 86
5.3.1.3
Cycle Type / Direction (CYCTYPE + DIR)......................... 87
5.3.1.4
SIZE .................................................................................. 87
5.3.1.5
SYNC ................................................................................ 88
5.3.1.6
SYNC Time-out ................................................................. 88
5.3.1.7
SYNC Error Indication ....................................................... 89
5.3.1.8
LFRAME# Usage .............................................................. 89
5.3.1.9
I/O Cycles.......................................................................... 90
5.3.1.10 Bus Master Cycles ............................................................ 90
5.3.1.11 LPC Power Management .................................................. 91
5.3.1.12 Configuration and Intel® ICH3 Implications ....................... 91
5.4
DMA Operation (D31:F0) ............................................................................... 91
5.4.1
Channel Priority ................................................................................ 92
5.4.1.1
Fixed Priority ..................................................................... 92
5.4.1.2
Rotating Priority................................................................. 93
5.4.2
Address Compatibility Mode ............................................................. 93
5.4.3
Summary of DMA Transfer Sizes ..................................................... 93
5.4.3.1
Address Shifting When Programmed for 16-Bit I/O
Count by Words................................................................. 93
5.4.4
Autoinitialize...................................................................................... 94
5.4.5
Software Commands ........................................................................ 94
5.4.5.1
Clear Byte Pointer Flip-Flop .............................................. 94
5.4.5.2
DMA Master Clear............................................................. 94
5.4.5.3
Clear Mask Register .......................................................... 94


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