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HT82A832R Datasheet(PDF) 11 Page - Holtek Semiconductor Inc

Part # HT82A832R
Description  USB Audio MCU
Download  51 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82A832R Datasheet(HTML) 11 Page - Holtek Semiconductor Inc

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HT82A832R
Rev. 1.10
11
June 15, 2007
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
The play interrupt is initialized by setting the play
interrupt request flag (bit 4 of INTC1), caused by a play
data valid. When the interrupt is enabled, the stack is not
full and the PLAYF is set, a subroutine call to location
10H will occur. The related interrupt request flag
(PLAYF) will be reset and the EMI bit cleared to disable
further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL
register) is set to
²1², the play interrupt frequency will
change to 8KHz, otherwise the interrupt frequency is
48kHz.
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 5 of INTC1), that is generated by the
reception or transfer of a complete 8-bits of data
between the HT82A832R and the external device. The
serial interface interrupt is controlled by setting the
Serial interface interrupt control bit (ESII; bit 1 of
INTC1). After the interrupt is enabled (by setting SBEN;
bit 4 of SBCR), and the stack is not full and the SIF is set,
a subroutine call to location 14H occurs.
The record interrupt is initialized by setting the record
interrupt request flag (bit 6 of INTC1), caused by a
record data valid. When the interrupt is enabled, the
stack is not full and RECF is set, a subroutine call to
location 18H will occur. The related interrupt request flag
(RECF) will be reset and the EMI bit cleared to disable
further interrupts. If ADC powered down (AD_ENB =1)
or USB clock disabled (USBCKEN=0), the record
interrupt will be disabled.
During the execution of an interrupt subroutine, other
interrupt acknowledge signals are held until the
²RETI²
instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine,
²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous
requests the following table shows the priority that is
applied. These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Play Interrupt
4
10H
Serial Interface Interrupt
5
14H
Record Interrupt
6
18H
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be
damaged once the
²CALL² operates in the interrupt
subroutine.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
USBF
USB interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as
²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
EPLAYI
Play interrupt (1=enable; 0=disable)
1
ESII
Control Serial interface interrupt (1=enable; 0=disable)
2
RECI
Record interrupt (1=enable; 0=disable)
3, 7
¾
Unused bit, read as
²0²
4
PLAYF
Play interrupt request flag (1=active; 0=inactive)
5
SIF
Serial interface interrupt request flag (1=active; 0=inactive)
6
RECF
Record interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register


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