SN74LVC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS301 – JANUARY 1993 – REVISED MARCH 1994

Copyright

7–1

POST OFFICE BOX 655303

CMOS) Submicron Process

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

This octal edge-triggered D-type flip-flop is

The SN74LVC574 features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at

the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

The output-enable (OE) input does not affect the internal operations of the flip-flops. Old data can be retained

or new data can be entered while the outputs are in the high-impedance state.

The SN74LVC574 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE

CLK

D

Q

L

↑

H

H

L

↑

LL

L

LX

Q0

H

X

X

Z

DB, DW, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

CLK

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PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.