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EM44BM1684LBC-37FE Datasheet(PDF) 4 Page - Eorex Corporation |
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EM44BM1684LBC-37FE Datasheet(HTML) 4 Page - Eorex Corporation |
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4 / 29 page  eorex EM44AM1684LBC Jul. 2006 www.eorex.com 4/29 Pin Description (Simplified) Pin Name Function J8,K8 CK,/CK (System Clock) CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). L8 /CS (Chip Select) All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. K2 CKE (Clock Enable) CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self- Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE are disabled during Self-Refresh. M8,M3,M7,N2,N8, N3,N7,P2,P8,P3, M2,P7,R2 A0~12 (Address) Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. L2,L3 BA0, BA1 (Bank Address) BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. K9 ODT (On Die Termination) ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. K7, L7, K3 /RAS, /CAS, /WE (Command Inputs) /RAS, /CAS and /WE (along with /CS) define the command being entered. B7,A8,F7,E8 UDQS,/UDQS, LDQS,/LDQS (Data Strobe) Output with read data, input with write data. Edge-aligned with read data, centered in write data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary signals /LDQS and /UDQS |
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