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PGA113 Datasheet(PDF) 4 Page - Texas Instruments |
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PGA113 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 38 page  www.ti.com PGA112 ,, PGA113 PGA116, PGA117 SBOS424 – MARCH 2008 ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted. PGA112, PGA113 PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT Voltage Output Swing from Rail IOUT = ±0.25mA, AVDD ≥ DVDD (6) GND + 0.05 DVDD – 0.05 V IOUT = ±5mA, AVDD ≥ DVDD (6) GND + 0.25 DVDD – 0.25 V DC Output Nonlinearity VOUT = GND + 85mV to DVDD – 85mV (7) 0.0015 %FSR Short-Circuit Current ISC –30/+60 mA Capacitive Load Drive CLOAD See Typical Characteristics NOISE Input Voltage Noise Density en f > 10kHz, CL = 100pF, VS = 5V 12 nV/ √Hz f > 10kHz, CL = 100pF, VS = 2.2V 22 nV/ √Hz Input Voltage Noise en f = 0.1Hz to 10Hz, CL = 100pF, VS = 5V 0.362 µV PP f = 0.1Hz to 10Hz, CL = 100pF, VS = 2.2V 0.736 µV PP Input Current Density In f = 10kHz, CL = 100pF 400 fA/ √Hz SLEW RATE Slew Rate SR See Table 1 V/ µs SETTLING TIME Settling Time tS See Table 1 µs FREQUENCY RESPONSE Frequency Response See Table 1 MHz THD + NOISE G = 1, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.003 % G = 10, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.005 % G = 50, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.03 % G = 128, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.08 % G = 200, f = 1kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.1 % G = 1, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.02 % G = 10, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.01 % G = 50, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.03 % G = 128, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.08 % G = 200, f = 20kHz, VOUT = 4VPP at 2.5VDC, CL = 100pF 0.11 % POWER SUPPLY Operating Voltage Range (6) AVDD 2.2 5.5 V DVDD 2.2 5.5 V Quiescent Current Analog IQA IO = 0, G = 1, VOUT = VREF 0.33 0.45 mA Over Temperature, –40 °C to +125°C 0.45 mA IO = 0, G = 1, VOUT = VREF, SCLK at 10MHz, Quiescent Current Digital (8) (9) (10) IQD 0.75 1.2 mA CS = Logic 0, DIO = Logic 0 IO = 0, G = 1, VOUT = VREF, SCLK at 10MHz, Over Temperature, –40 °C to +125°C(8)(9)(10) 1.2 mA CS = Logic 0, DIO = Logic 0 Shutdown Current Analog + Digital (8) (9) ISDA + ISDD IO = 0, VOUT = VREF, G = 1, SCLK Idle 4 µA IO = 0, VOUT = 0, G = 1, SCLK at 10MHz, 245 µA CS = Logic 0, DIO = Logic 0 POWER-ON RESET (POR) Digital interface disabled and Command Register set to POR POR Trip Voltage 1.6 V values for DVDD < POR Trip Voltage (6) When AVDD is less than DVDD, the output is clamped to AVDD + 300mV. (7) Measurement limited by noise in test equipment and test time. (8) Does not include current into or out of the VREF pin. Internal RF and RI are always connected between VOUT and VREF. (9) Digital logic levels: DIO = logic 0. 10 µA internal current source. (10) Includes current from op amp output structure. 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113 |
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