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PI90SD1636CFDE Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation |
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PI90SD1636CFDE Datasheet(HTML) 9 Page - Pericom Semiconductor Corporation |
9 / 15 page 9 PS8922A 11/08/07 PI90SD1636C SERDES Gigabit Ethernet Transceiver Table 9. Receiver Timing Characteristics TA = 0°C to +70°C, VCC = 3.15V to 3.45V Symbol Parameter Min. Typ. Max. Unit b_sync[1] Bit Sync Time 2500 bits f_lock Frequency Lock at Powerup 500 μs tSETUP Data Setup Before Rising Edge of RX_CLK 2.5 ns tHOLD Data Hold After Rising Edge of RX_CLK 1.5 tDUTY RX_CLK Duty Cycle 40 60 % tA-B RX_CLK Skew 7.5 8.5 ns T_rxlat[2] Receiver Latency 22.4 ns 28.0 bits DATA DATA DATA TX<9:0> TX_CLK tHOLD tSETUP 1.4V 2.0V 0.8V DATA DATA Figure 3. Transmitter Section Timing T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 DATA BYTE A DATA BYTE B DATA BYTE B DATA BYTE C 1.4V DOUT± TX<9:0> TX_CLK t_TXLAT Figure 4. Transmitter Latency Notes: 1. This is the recovery for input phase jumps. 2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0). 07-0253 |
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