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M28C17-120MS6T Datasheet(PDF) 3 Page - STMicroelectronics |
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M28C17-120MS6T Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 17 page Symbol Parameter Value Unit TA Ambient Operating Temperature – 40 to 125 °C TSTG Storage Temperature Range – 65 to 150 °C VCC Supply Voltage – 0.3 to 6.5 V VIO Input/Output Voltage – 0.3 to VCC +0.6 V VI Input Voltage – 0.3 to 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) (2) 4000 V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500 Ω; MIL-STD-883C, 3015.7 Table 2. Absolute Maximum Ratings (1) Mode E G W DQ0 - DQ7 Standby 1 X X Hi-Z Output Disable X 1 X Hi-Z Write Disable X X 1 Hi-Z Read 0 0 1 Data Out Write 0 1 0 Data In Chip Erase 0 V 0 Hi-Z Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH; V = 12 ± 5%. Table 3. Operating Modes (1) OPERATION In order to prevent data corruption and inadvertent write operations an internal VCCcomparator inhibits Write operation if VCC is below VWI (see Table 7). Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C17 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high. Write Write operations are initiated when both W and E are low and G is high.The M28C17 supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 64 bytes to be consecu- tively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a mini- mum data transfer rate of 1/tWHWH (see Figure 13). If a transition of E or W is not detected within tWHWH, the internal programming cycle will start. Chip Erase The contents of the entire memory may be erased to FFh by use of the Chip Erase command by setting Chip Enable (E) Low and Output Enable (G) to VCC + 7.0V. The chip is cleared when a 10ms low pulse is applied to the Write Enable pin. 3/17 M28C17 |
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