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M28C17-90WK1TR Datasheet(PDF) 5 Page - STMicroelectronics |
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M28C17-90WK1TR Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 17 page 5/17 M28C16B, M28C17B ignored, and have no effect on the memory con- tents. The device remains in this mode until a valid Soft- ware Data Protection disable sequence is re- ceived. The device reverts to its “unprotected” state. The status of the Software Data Protection (en- abled or disabled) is represented by a non-volatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Similarly to disable the Software Data Protection, the user has to write specific data bytes into six dif- ferent locations, as shown in Figure 6. This com- plex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism. Figure 4. Software Data Protection Enable Algorithm and Memory Write Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations. AI02819 Write AAh in Address 555h Write 55h in Address 2AAh Write A0h in Address 555h SDP is set Write AAh in Address 555h Write 55h in Address 2AAh Write A0h in Address 555h Page Write (1 up to 64 bytes) Write to Memory When SDP is SET SDP Enable Algorithm Page Write Timing (see note 1) Page Write Timing (see note 1) Write is Enabled Physical Page Write Instruction Figure 5. Status Bit Assignment AI02815 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DP TB PLTS Hi-Z DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 = Data Polling = Toggle Bit = Page Load Timer Status = High impedance Figure 6. Software Data Protection Disable Algorithm AI02820 Write AAh in Address 555h Write 55h in Address 2AAh Write 80h in Address 555h Unprotected State Write AAh in Address 555h Write 55h in Address 2AAh Write 20h in Address 555h Page Write Timing |
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