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EM620FV16B Series
Low Power, 128Kx16 SRAM
9
tWC
Address
CS1
CS2
UB,LB
WE
Data in
Data out
tCW(2)
tWR(4)
tAW
tBW
tWP(1)
tDW
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
High-Z
High-Z
Data Valid
tAS(3)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 a high CS2 and low WE. A write begins at the lastest transition among CS1
goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes high and WE
goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high.
tWC
Address
CS1
CS2
WE
Data in
Data out
tCW(2)
tWR(4)
tAW
tWP(1)
tDW
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
High-Z
High-Z
Data Valid
tAS(3)