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SN65HVD379 Datasheet(PDF) 1 Page - Texas Instruments |
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SN65HVD379 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 14 page www.ti.com FEATURES DESCRIPTION APPLICATIONS VID RecevierOutputHigh ReceiverOutputLow R D B A Z Y 7 8 6 5 2 3 DP (TOP VIEW) ACKAGE 1 2 3 4 8 7 6 5 R D VCC B A Z Y GND SN65HVD379 SLLS667A – FEBRUARY 2006 – REVISED MAY 2006 3.3 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS • Designed for INTERBUS Applications The SN65HVD379 is a differential line driver and differential-input line receiver that operates with a • Balanced Receiver Thresholds 3.3-V power supply. Each driver and receiver has • 1/2 Unit-Load (up to 64 nodes on the bus) separate input and output pins for full-duplex bus • Bus-Pin ESD Protection 15 kV HBM communication designs. They are designed for • Bus-Fault Protection of –7V to 12V balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and • Thermal Shutdown Protection ISO 8482:1993 standard-compliant devices. • Power-Up/Down Glitch-free Bus Inputs and These differential bus drivers and receivers are Outputs monolithic, integrated circuits designed for full-duplex • High Input Impedance with Low VCC bi-directional data communication on multipoint • Monotonic Outputs During Power Cycling bus-transmission lines at signaling rates(1) up to 25 Mbps. The SN65HVD379 is fully enabled with no • 5V Tolerant Inputs external enabling pins. The 1/2 unit load receiver has a higher receiver input • Digital Motor Control resistance. This results in lower bus leakage currents over the common-mode voltage range, and reduces • Utility Meters the total amount of current that an RS-485 driver is • Chassis-to-Chassis Interconnections forced to source or sink when transmitting. • Electronic Security Stations The balanced differential receiver input threshold • Industrial, Process, and Building Automation makes the SN65HVD379 more compatible with • Point-of-Sale (POS) Terminals and Networks fieldbus requirements that define an external failsafe • DTE/DCE Interfaces structure. (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). BALANCED RECEIVER INPUT THRESHOLDS SN65HVD379 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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