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M29F512B70NZ1T Datasheet(PDF) 4 Page - STMicroelectronics |
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M29F512B70NZ1T Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 16 page  M29F512B 4/16 Table 3. Bus Operations Note: X = VIL or VIH. Operation E G W Address Inputs Data Inputs/Outputs Bus Read VIL VIL VIH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH VIH XHi-Z Standby VIH XX X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 20h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 24h Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 3, Bus Operations. COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 4, Com- mands. Refer to Table 4 in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Chip Erase operation the memory will take about 10µs to abort the Chip Erase. During the abort pe- riod no valid data can be read from the memory. Issuing a Read/Reset command during a Chip Erase operation will leave invalid data in the mem- ory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code and the Device Code. Three consecutive Bus Write op- erations are required to issue the Auto Select com- mand. Once the Auto Select command is issued the memory remains in Auto Select mode until an- other command is issued. |
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