PDSP16256

2

DA15:0

16-bit data input bus to Network A.

DB15:0

Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a

cascaded chain. Input to Network B in the dual filter modes.

X31:0

Expansion input bus in the single filter mode. Connected to the previous filter output in a cascaded chain.

The inputs are not used on a single device system or on the Termination device in a cascaded chain. The

X bus provides the output from Network B in both dual modes.

F31:0

In single filter mode this bus holds the main device output. In dual mode it holds the output from Network A.

FEN

Filter enable. The first high present on an SCLK rising edge defines the first data sample. The signal must

stay active whilst valid data is being received and must be low if FRUN is high.

DFEN

Delayed filter enable. This output is connected to the Filter Enable input of the next device in a cascaded

chain when moving towards the termination device and with multiple stand-alone EPROM-loaded

configurations. It is used to coordinate the control logic within each device.

SWAP

Selects either the upper or lower set of coefficients for Bank Swap. A low selects the lower bank, a high the

upper bank.

FRUN

In EPROM load mode, when high this signal allows continuous filter operations to occur without the need for

the initial FEN edge. If the device is not a single, interface or master device then this pin must be tied low.

low for a single cycle, signal BUSY will indicate when the internal clearing is complete. After a clear the

device must be re-synchronised to the data stream using FEN. It is recommended that FEN is taken low

at the same time as clear. FEN may then be taken high to synchronise the data stream once BUSY has

returned low.

C15:0

16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the

text.

A7:0

Coefficient address bus. In the EPROM mode A7:0 are address outputs for an EPROM. In the remote host

mode they are inputs from the host. A7 is not used when coefficients are loaded as 16-bit words.

CCS

This pin is similar in operation to A7:0 and provides a higher order address bit. When low the coefficients

are loaded, when high the control register is loaded.

In the remote mode this pin is an input which when low enables the load operation. In the EPROM mode

it is an output which provides the write enable for other slave devices.

This pin is always an input and must also be low for the internal write operation to occur.

When this pin is tied low, coefficients are loaded as two 8-bit bytes. When the pin is high they are loaded

as 16-bit words. In the EPROM mode this pin is ignored.

When this pin is tied low coefficients are loaded as bytes from an external EPROM. The device outputs an

address on A7:0. When the pin is high coefficients must be loaded from a remote master. They can then

be transferred individually rather than as a complete set.

SCLK

The main system clock; all operations are synchronous with this clock. The clock rate must be either 1, 2,

4, or 8 times the required data sampling rate. The factor used depends on the required filter length.

CLKOP

This output, when used to enable SCLK, can provide a data sampling clock. It has the effect of dividing the

SCLK rate by 1, 2, 4 or 8 depending on the filter mode selected.

device and does not therefore take effect until the first SCLK rising edge

BUSY

A high on this signal indicates that the device is completing internal operations and is not yet able to accept

new data. The signal is used during automatic EPROM loading, reset and accumulator clearing.

When this pin is low the control logic and accumulators are reset. In the EPROM mode it will initiate a load

sequence when it goes high.

Signal

Description

Table 1 Pin descriptions

NOTES

1. Unused buses (e.g. X31:0 when the device is configured in single or termination mode) can be set to any value. They should however be

maintained at a valid logic level to avoid an increase in power consumption.

DCLR

WEN

CS

BYTE

EPROM

OEN

RES