PDSP16318/13618A

3

Symbol

A15:0

B15:0

C15:0

D15:0

CLK

CEA

CEB

OEC

OED

OVR

ASR1:0

ASI1:0

CLR

MS

S2:0

DEL

VCC

GND

Description

Data presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.

Data presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB

and has the same weighting as A15.

New data appears on this output after the rising edge of CLK. C15 is the MSB.

New data appears on this output after the rising edge of CLK. C15 is the MSB.

Common Clock to all internal registers

Clock enable: when low the clock to the A input register is enabled.

Clock enable: when low the clock to the B input register is enabled.

Output enable: Asynchronous 3-state output control: The C outputs are in a high impedance

state when this input is high.

Output enable: Asynchronous 3-state output control: The D outputs are in a high impedance

state when this input is high.

Overflow flag: This flag will go high in any cycle during which either the output data overflows the number

range selected or either of the adder results overflow. A new OVR appears after the rising edge of the

CLK.

Add/subtract Real: Control input for the 'Real' adder. This input is latched by the rising edge of clock.

Add/subtract Imag: Control input for the 'Imag' adder. This input is latched by the rising edge of clock.

Accumulator Clear: Common accumulator clear for both Adder/Subtractor units. This input is latched by

the rising edge of CLK.

Mux select: Control input for both adder multiplexers. This input is latched by the rising edge of CLK.

When high the feedback path is selected.

Scaling control: This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.

This input is latched by the rising edge of CLK.

Delay Control: This input selects the delayed input to the real adder for operations involving the

PDSP16112. This input is latched by the rising edge of CLK.

+5V supply: Both Vcc pins must be connected.

0V supply: Both GND pins must be connected.

Type

Input

Input

Output

Output

Input

Input

Input

Input

Input

Output

Input

Input

Input

Input

Input

Input

Power

Ground

GG pin

77

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

5

AC pin

B2

C2

B1

C1

D2

D1

E3

E2

E1

F2

F3

G3

G1

G2

F1

H1

H2

J1

K1

J2

L1

Function

D7

D8

D9

D10

GND

VCC

D11

D12

D13

D14

D15

C15

C14

C13

C12

VCC

GND

C11

C10

C9

C8

GG pin

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

AC pin

K2

K3

L2

L3

K4

L4

J5

K5

L5

K6

J6

J7

L7

K7

L6

L8

K8

L9

L10

K9

L11

Function

C7

C6

C5

C4

C3

C2

C1

C0

OED

OEC

S2

S1

S0

MS

ASI1

ASI0

DEL

CLR

ASR1

ASR0

A0

GG pin

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

AC pin

K10

J10

K11

J11

H10

H11

F10

G10

G11

G9

F9

F11

E11

E10

E9

D11

D10

C11

B11

C10

A11

Function

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

CEA

B15

B14

B13

B12

B11

GG pin

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

AC pin

B10

B9

A10

A9

B8

A8

B6

B7

A7

C7

C6

A6

A5

B5

C5

A4

B4

A3

A2

B3

A1

Function

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

CLK

CEB

OVR

D0

D1

D2

D3

D4

D5

D6

Device Pinout for ceramic 84 - pin PGA (AC84) and ceramic QFP (GG100)