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M28F101-70P3 Datasheet(PDF) 5 Page - STMicroelectronics |
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M28F101-70P3 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 23 page  AI01275 3V SRAM Interface 0V 1.5V 2.4V EPROM Interface 0.45V 2.0V 0.8V Figure 3. AC Testing Input Output Waveform AI01276 1.3V OUT CL = 30pF or 100pF CL = 30pF for SRAM Interface CL = 100pF for EPROM Interface CL includes JIG capacitance 3.3k Ω 1N914 DEVICE UNDER TEST Figure 4. AC Testing Load Circuit SRAM Interface Levels EPROM Interface Levels Input Rise and Fall Times ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0.45V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V Table 6. AC Measurement Conditions Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance VIN =0V 6 pF COUT Output Capacitance VOUT =0V 12 pF Note: 1. Sampled only, not 100% test.ed Table 7. Capacitance (1) (TA =25 °C, f = 1 MHz ) A write to the command register is made by bringing W Low while E is Low. The falling edge of W latches Addresses, while the rising edge latches Data, which are used for those commands that require address inputs, command input or provide data output. The supply voltage VCC and the program voltage VPP can be applied in any order. When the device is powered up or when VPP is ≤ 6.5V the contents of the command register defaults to 00h, thus automatically setting-up Read operations. In addi- tion a specific command may be used to set the command register to 00h for reading the memory. The system designer may chose to provide a con- stant high VPP and use the register commands for all operations, or to switch the VPP from low to high only when needing to erase or program the mem- ory. All command register access is inhibited when VCC falls below the Erase/Write Lockout Voltage (VLKO) of 2.5V. If the device is deselected during Erasure, Pro- gramming or Verification it will draw active supply currents until the operations are terminated. The device is protected against stress caused by long erase or program times. If the end of Erase or Programming operations are not terminated by a Verify cycle within a maximum time permitted, an internal stop timer automatically stops the opera- tion. The device remains in an inactive state, ready to start a Verify or Reset Mode operation. READ/WRITE MODES (cont’d) 5/23 M28F101 |
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