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M28C64-20WKA1T Datasheet(PDF) 4 Page - STMicroelectronics |
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M28C64-20WKA1T Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 24 page  M28C64 4/24 Table 3. Operating Modes 1 Note: 1. 0= VIL;1=VIH;X = VIH or VIL; V=12V ± 5%. Mode E G W DQ0-DQ7 Stand-by 1 X X Hi-Z Output Disable X 1 X Hi-Z Write Disable X X 1 Hi-Z Read 0 0 1 Data Out Write 0 1 0 Data In Chip Erase 0 V 0 Hi-Z SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A12). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. Write Enable (W). The Write Enable input controls whether the addressed location is to be read, from or written to. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. DEVICE OPERATION In order to prevent data corruption and inadvertent write operations, an internal VCC comparator inhibits the Write operations if the VCC voltage is lower than VWI (see Table 4A and Table 4B). Once the voltage applied on the VCC pin goes over the VWI threshold (VCC>VWI), write access to the memory is allowed after a time-out tPUW,as specified in Table 4A and Table 4B. Further protection against data corruption is offered by the E and W low pass filters: any glitch, on the E and W inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. Table 4A. Power-Up Timing1 for M28C64 (5V range) (TA = 0 to 70 °C or –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V) Note: 1. Sampled only, not 100% tested. Table 4B. Power-Up Timing1 for M28C64-xxW (3V range) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V) Note: 1. Sampled only, not 100% tested. Symbol Parameter Min. Max. Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI)10 ms VWI Write Inhibit Threshold 3.0 4.2 V Symbol Parameter Min. Max. Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI)15 ms VWI Write Inhibit Threshold 1.5 2.5 V |
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