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ISPGDX160A-5B272 Datasheet(PDF) 5 Page - Lattice Semiconductor |
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ISPGDX160A-5B272 Datasheet(HTML) 5 Page - Lattice Semiconductor |
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5 / 23 page  5 Specifications ispGDX Family Figure 4. Data Bus Byte Swapper Figure 5. Four-Port Memory Interface Designing with the ispGDX As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as output. For the case of PDP applications, the designer does have to take into consideration the limitations on pins that can be used as control (MUX0, MUX1, OE, CLK) or data (MUXA-D) inputs. The restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. The MUXA-D input partitioning requires that designers consciously assign pinouts so that MUX inputs are in the appropriate, disjoint groups. For example, since the MUXA group includes I/O0-19 (80 I/O device), it is not possible to use I/O0 and I/O9 in the same MUX function. As previously discussed, data path functions will be assigned early in the design process and these restric- tions are reasonable in order to optimize speed and cost. User Electronic Signature The ispGDX Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. The UES information is accessible through the boundary scan or Lattice ISP programming port via a specific command. This information can be read even when the security cell is programmed. Security Bit The ispGDX Family includes a security bit feature that prevents reading the device program once set. Even when set, it does not inhibit reading the UES or device ID code. It can be erased only via a device bulk erase. Applications (Cont.) OEA OEB I/OA D0-7 D8-15 D8-15 D0-7 I/OB XCVR OEA OEB I/OA I/OB XCVR OEA OEB I/OA I/OB XCVR OEA OEB I/OA I/OB XCVR Port #1 OE1 Memory Port OEM SEL0 SEL1 To Memory Port #2 OE2 Port #3 OE3 Note: All OE and SEL lines driven by external arbiter logic (not shown). Port #4 OE4 4-to-1 16-Bit MUX Bidirectional Figure 3. Address Demultiplex/Data Buffering DQ CLK OEA OEB I/OA I/OB Address Buffered Data To Memory/ Peripherals XCVR Address Latch |
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