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ISPGDX160A-7B272 Datasheet(PDF) 9 Page - Lattice Semiconductor

Part # ISPGDX160A-7B272
Description  In-System Programmable Generic Digital Crosspoint
Download  23 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPGDX160A-7B272 Datasheet(HTML) 9 Page - Lattice Semiconductor

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Specifications ispGDX Family
-5
-7
PARAMETER #2
DESCRIPTION1
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
21 Input Buffer Delay
0.7
1.3
ns
GRP
tgrp
22 GRP Delay
2.0
2.5
ns
MUX
tmuxd
23 I/O Cell MUX A/B/C/D Data Delay
1.0
1.4
ns
tmuxs
24 I/O Cell MUX A/B/C/D Data Select
2.5
3.4
ns
Register
tiolat
25 I/O Latch Delay
1.6
2.2
ns
tiosu
26 I/O Register Setup Time Before Clock
1.6
1.8
ns
tioh
27 I/O Register Hold Time After Clock
2.4
3.6
ns
tioco
28 I/O Register Clock to Output Delay
1.6
2.2
ns
tior
29 I/O Reset to Output Delay
0.7
1.0
ns
Data Path
trfdbk
30 I/O Register Feedback Delay
0.2
0.3
ns
tiobp
31 I/O Register Bypass Delay
0.4
0.6
ns
tioob
32 I/O Register Output Buffer Delay
0.1
0.7
ns
tmuxc (Yx Clk) 33 I/O Register Data Input MUX Delay
1.1
1.2
ns
tmuxc (I/O Clk) 34 I/O Register Data Input MUX Delay
2.1
3.2
ns
tiod (Yx Clk)
35 I/O Register I/O Input MUX Delay
4.1
5.1
ns
tiod (I/O Clk) 36 I/O Register I/O Input MUX Delay
5.1
7.1
ns
Outputs
tob
37 Output Buffer Delay
0.9
1.3
ns
tobs
38 Output Buffer Delay, Slow Slew
5.9
8.3
ns
toen
39 I/O Cell OE to Output Enabled
0.8
1.1
ns
toedis
40 I/O Cell OE to Output Disabled
0.8
1.1
ns
tgoe
41 Global Output Enable Delay
2.5
3.6
ns
ttoe
42 Test OE Enable Delay
8.2
10.9
ns
Clocks
tcio
43 I/O Clock Delay
0.7
1.0
ns
tgy0/1/2/3
44 Clock Delay, Y0/1/2/3
2.4
2.8
ns
Global Reset
tgr
45 Global Reset to I/O Register/Latch
12.3
15.0
ns
Internal Timing Parameters1
Over Recommended Operating Conditions
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.


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