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M29W004B-150N6TR Datasheet(PDF) 3 Page - STMicroelectronics |
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M29W004B-150N6TR Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 30 page Memory Blocks The devices feature asymmetrically blocked archi- tecture providing system memory integration. Both M29W004T and M29W004B devices have an array of 11 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and seven Main Blocks of 64K Bytes. The M29W004T has the Boot Block at the top of the memory address space and the M29W004B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unpro- tected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write com- mand, Output Disable, Standby, Reset, Block Pro- t e c t ion, Unpr ot e c t ion, Pr ot ec t ion Ve r if y, Unprotection Verify and Block Temporary Unpro- tection. See Tables 4 and 5. Command Interface Instructions, made up of commands written in cy- cles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Pro- gram/Erase Controller instructions. The ’Com- mand’ itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command se- quence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all tim- ing and verification of the Program and Erase operations. The Status Register Data Polling, Tog- gle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instruc- tions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instruc- tions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if Vcc falls below VLKO, the command interface is reset to Read Array. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write opera- tion on the falling edge of Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or De- vice Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled de- pending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a com- mand to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection opera- tion. 3/30 M29W004T, M29W004B |
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