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M29W008AB120N6T Datasheet(PDF) 5 Page - STMicroelectronics |
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M29W008AB120N6T Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 30 page  5/30 M29W008AT, M29W008AB SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A19). The address inputs for the memory array are latched during a write op- eration on the falling edge of Chip Enable E or Write Enable W. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled de- pending on the combination of levels on A0, A1 A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write En- able W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high im- pedance when the chip is deselected or the out- puts are disabled and when RP is at a Low level. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E High deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Un- protection operation. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read op- eration. When G is High the outputs are High im- pedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Ready/Busy Output (RB). Ready/Busy is an open-drain output and gives the internal state of the P/E.C. of the device. When RB is Low, the de- vice is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend in- struction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Stand-by modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and pro- tected block(s) temporary unprotection functions. Reset of the memory is achieved by pulling RP to VIL for at least tPLPX. When the reset pulse is giv- en, if the memory is in Read or Stand-by modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Pro- gram modes the reset will take tPLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Pro- gram operation will corrupt the data being pro- grammed or the sector(s) being erased. See Tables 15, 16 and Figure 8. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transi- tion of RP from VIH to VID must slower than tPH- PHH. (See Tables 17, 18 and Figure 8). When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. |
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