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M34S32MN Datasheet(PDF) 7 Page - STMicroelectronics |
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M34S32MN Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 18 page M34S32 7/18 EEPROM Addressing. A data byte in the memory is addressed through 2 bytes of address informa- tion. The Most Significant Byte is sent first and the Least significant Byte is sent after. Bits b15 to b0 form the address of any byte of the memory. Bits b15 to b12 are don’t care on the M34S32 series. Figure 7. AC Waveforms Table 9. Most Significant Byte b15 b14 b13 b12 b11 b10 b9 b8 XX X X 4. b15 to b12 are Don’t Care. Table 10. Least Significant Byte b7 b6 b5 b4 b3 b2 b1 b0 SCL SDA IN SCL SDA OUT SCL SDA IN tCHCL tDLCL tCHDX START CONDITION tCLCH tDXCX tCLDX SDA INPUT SDA CHANGE tCHDH tDHDL STOP & BUS FREE DATA VALID tCLQV tCLQX DATA OUTPUT tCHDH STOP CONDITION tCHDX START CONDITION WRITE CYCLE tW AI00795B Write Operations Following a START condition the master sends a Device Select Byte with the RW bit reset to 0. The memory acknowledges this and waits for 2 bytes of address. These 2 address bytes (8 bits each) provide access to any of the memory location. Writing in the memory may be inhibited with WC pin and WCpol bit (see Table 13 and Figure 11). |
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