22-Bit, Low-Power, 5MHz to 10MHz

Serializer and Deserializer Chipset

8

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Pin Description (MAX9223)

PIN

NAME

FUNCTION

1–12, 14, 15,

21–28

DIN13–DIN2,

DIN1, DIN0,

DIN21–DIN14

Single-Ended Parallel Data Inputs. The 22 data bits are loaded into the input latch on the rising

edge of PCLKIN. DIN[9:0] are 1.71V to 3.465V tolerant. Internally pulled down to GND.

13

PCLKIN

Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel

data input. Internally pulled down to GND.

16

PWRDN

Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode.

Drive PWRDN high for normal operation. Internally pulled down to GND.

17

SDO-

Inverting LCDS Serial-Data Output

18

SDO+

Noninverting LCDS Serial-Data Output

19

GND

Ground

20

Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to

the device as possible, with the smallest value capacitor closest to the supply pin.

—

EP

Exposed Paddle. Connect EP to ground.

Pin Description (MAX9224)

PIN

NAME

FUNCTION

1, 7, 8, 10–28

DOUT21,

DOUT0, DOUT1,

DOUT2–DOUT20

Single-Ended Parallel Data Outputs. DOUT[21:0] are valid on the rising edge of PCLKOUT.

Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to

the device as possible, with the smallest value capacitor closest to the supply pin.

3

GND

Ground

4

SDI+

Noninverting LCDS Serial-Data Input

5

SDI-

Inverting LCDS Serial-Data Input

Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to

the device as possible, with the smallest value capacitor closest to the supply pin.

9

PCLKOUT

Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically

the pixel clock).

—

EP

Exposed Paddle. Connect EP to ground.