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M36W108T120ZM1T Datasheet(PDF) 6 Page - STMicroelectronics |
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M36W108T120ZM1T Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 35 page M36W108T, M36W108B 6/35 FLASH MEMORY COMPONENT Organization and Architecture Organization. The Flash chip is organized as 1Mbit x 8. The memory uses the address inputs A0-A19 and the Data Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable (EF), Output Enable (G) and Write Enable (W) inputs. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, while Status Register data out- puts on DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C. operations. A Ready/Busy (RB) output indicates the completion of the internal algorithms. Memory Blocks. The device features asymmetri- cally blocked architecture providing system mem- ory integration. Both Top and Bottom Boot Block devices have an array of 19 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and fifteen Main Blocks of 64K Bytes. The Top Boot Block version has the Boot Block at the top of the mem- ory address space and the Bottom Boot Block ver- sion locates the Boot Block starting at the bottom. The memory maps and block address tables are showed in Figures 4, 5 and Tables 4, 5. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase opera- tions are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not be- ing erased, and then resumed. Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write command, Output Disable, Standby and Reset (see Table 6). Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature or the Status Register. Both Chip Enable (EF) and Output Enable (G) must be low, with Write Enable (W) high, in order to read the output of the memory. Table 4. Top Boot Block, Flash Block Address Size (KWord) Address Range 16 FC000h-FFFFFh 8 FA000h-FBFFFh 8 F8000h-F9FFFh 32 F0000h-F7FFFh 64 E0000h-EFFFFh 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 64 00000h-0FFFFh Table 5. Bottom Boot Block, Flash Block Address Size (KWord) Address Range 64 F0000h-FFFFFh 64 E0000h-EFFFFh 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 32 08000h-0FFFFh 8 06000h-07FFFh 8 04000h-05FFFh 16 00000h-03FFFh |
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