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M36W416BG85ZA1T Datasheet(PDF) 8 Page - STMicroelectronics |
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M36W416BG85ZA1T Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 62 page  M36W416TG, M36W416BG 8/62 SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable (ES) and Write Enable (WS) signals. Address Inputs (A18-A19). Addresses A18-A19 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able (EF) and Write Enable (WF) signals Data Inputs/Outputs (DQ0-DQ15). The Data I/ O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable controls the data outputs during the Bus Read op- eration of the Flash memory. Flash Write Enable (WF). The Write Enable con- trols the Bus Write operation of the Flash memo- ry’s Command Interface. The data and address inputs are latched on the rising edge of Chip En- able, EF, or Write Enable, WF, whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 6, Read Protection Register and Protection Register Lock). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is re- quired to ensure valid data outputs. SRAM Chip Enable (E1S, E2S). The Chip En- able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S or E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL and, E1S at VIL or E2S at VIL at the same time. SRAM Write Enable (WS). The Write Enable in- put controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VDDF and VDDS Supply Voltages. VDDF pro- vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQF and VDDS Supply Voltage (2.7V to 3.3V). VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control pins. This allows all Outputs to be powered independently of the Flash core power supply, VDDF. VDDQF can be tied to VDDS. VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. The Supply Volt- age VDDF and the Program Supply Voltage VPPF can be applied in any order. If VPPF is kept in a low voltage range (0V to 3.6V) VPPF is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPPF > VPP1 en- ables these functions (see Table 6, DC Character- istics for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. If VPPF is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is com- pleted (see Table 19 and 20). |
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