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TLK2208B Datasheet(PDF) 2 Page - Texas Instruments |
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TLK2208B Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 40 page  TLK2208B 8PORT GIGABIT ETHERNET TRANSCEIVER SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006 2 WWW.TI.COM description (continued) The TLK2208B aligns the recovered data clock frequency to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that inserts or drops 20-bit IDLE codes as needed in the interpacket gap (IPG). In synchronous mode, the received data for all channels is aligned to a single receive data clock that is a buffered version of the reference clock. The TLK2208B supports a selectable IEEE 802.3z compliant 8b/10b encoder/decoder in all its modes of operation. The TLK2208B automatically locks onto incoming data without the need to pre-lock. The TLK2208B provides a comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported to aid in board-manufacturing testing. The TLK2208B is housed in a small form-factor 19 ×19-mm, 289-terminal BGA with 1,0-mm ball pitch. The ball out and footprint are compatible with those of the PMC-Sierra PM8352 8-channel transceiver.† The TLK2208B is characterized to support the commercial temperature range of 0 °C to 70°C. The TLK2208B consumes 1.3 W when operating at nominal conditions. The TLK2208B is designed to be hot-plug capable. A power-on reset puts the serial side output signal terminals TX+/TX− in the high-impedance state during power up. MAC/ Packet Processor 8 TX+ TX− RX+ RX− TDA..H[9:0] TCLKB RCLK 8 8 8 RDA..H[9:0] Electrical to Optical Array Switch Fabric 8 TX+ TX− RX+ RX− TDA..H[9:0] TCLKB RCLK 8 8 8 RDA..H[9:0] System Backplane Line Card 8 8 RDA..H[9:0] RCLK TCLKB TDA..H[9:0] 8 8 8 8 RX+ RX− TX+ TX− TLK2208B TLK2208B TLK2208B Figure 1. TLK2208B System Implementation Diagram † Functionally compatible with the PM8352 in multiplex channel mode. |
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