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M39208-15WNA1T Datasheet(PDF) 7 Page - STMicroelectronics |
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M39208-15WNA1T Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 30 page  Read the EEPROM Block Identifier The EEPROM block identifier (64 bytes, user de- fined) can be read with a single Read operation with A6 = ’0’ and A9 = VID (see Table 5). Read the OTP Row The OTP row is mapped in the EEPROM block (EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes) is by an instruction (see Table 4) composed of three specific Write operations of data bytes at three specific memory locations (each location in a dif- ferent page) before reading the OTP row content. When accessing the OTP row, only the LSB ad- dresses (A6 to A0) are decoded where A6 must be ’0’. Each Read of the OTP row has to be followed by the Return instruction (see Table 4). Read the Flash Sector Protection Status Reading the Flash sector protection status is by an instruction similar to the Read Manufacturer iden- tifier instruction, the only difference being the value of the logic levels applied on A0, A1, A6, while A16 and A17 define the Flash sector whose protection has to be verified. Such a read instruction will output a 01h if the Flash sector is protected and a 00h if the Flash sector is not protected. The Flash sector protection status can also be verified with a Read operation (see chapter: Flash block specific features), with VID on A9. Read the Status Bits The M39208 provides several Write operation status flags which may be used to minimize the application write (or erase or program) time. These signals are available on the I/O port bits when programming (or erasing) are in progress. Data Polling flag, DQ7. When Erasing or Pro- gramming into the Flash block (or when Writing into the EEPROM block), bit DQ7 outputs the comple- ment of the bit being entered for Program- ming/ Writing on DQ7. Once the Pr ogr am instruction or the Write operation is performed, the true logic value is read on DQ7 (in a Read opera- tion). Flash memory block specific features: – Data Polling is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. – During an Erase instruction, DQ7 outputs a ’0’. After completion of the instruction, DQ7 will out- put the last bit programmed (that is a ’1’ after erasing). – if the byte to be programmed is in a protected Flash sector, the instruction is ignored. – If all the Flash sectors to be erased are pro- tected, DQ7 will be set to ’0’ for about 100 µs, and then return to the previous addressed byte. No erasure will be performed. – if all sectors are protected, a Bulk Erase instruc- tion is ignored. Toggle flag, DQ6. The M39208 also offers another way for determining when the EEPROM write or the Flash memory Program instruction is com- pleted. During the internal Write operation, the DQ6 will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent attempts to read any byte of the memory, when either G , EE or EF is low. When the internal cycle is completed the toggling will stop and the data read on DQ0-DQ7 is the addressed memory byte. The device is now acces- sible for a new Read or Write operation. The opera- tion is completed when two successive reads yield the same output data. Flash memory block specific features: a. the Toggle bit is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). b. If the byte to be programmed belongs to a pro- tected Flash sector, the instruction is ignored and: EF EE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Flash VIL VIH Data Polling Toggle Flag Error Flag X Erase Time-out XX X EEPROM VIH VIL Data Polling Toggle Flag XX X X X X Note: X = Not guaranteed value, can be read either ’1’ or ’0’. Table 6. Status Bit 7/30 M39208 |
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