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M39208-10WNB1T Datasheet(PDF) 8 Page - STMicroelectronics |
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M39208-10WNB1T Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 30 page  – if all the Flash sectors selected for erasure are protected, DQ6 will toggle to ’0’ for about 100 µs, and then return to the previous ad- dressed byte. – if all sectors are protected, the Bulk Erase in- struction is ignored. Error flag, DQ5 (Flash block only). This bit is set to ’1’ when there is a failure during either a Flash byte programming or a Sector erase or the Bulk Erase. In case of error in Flash sector erase or byte program, the Flash sector in which the error oc- curred or to which the programmed byte belongs, must not be used any longer (other Flash sectors may still be used). The Error bit resets after Reset instruction. During a correct Program or Erase, the Error bit will set to ’0’. Erase Time-out flag, DQ3 (Flash block only). The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to ’0’ after a Sector Erase instruction for a time period of 100 µs ± 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to ’1’. WRITE a BYTE (or a PAGE) in EEPROM It should be noticed that writing in the EEPROM block is an operation, it is not an instruction (as for Programming a byte in the Flash block). Write a Byte in EEPROM Block A write operation is initiated when Chip Enable EE is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W, EE whichever occurs last. Once initiated, the write operation is internally timed until completion, that is during a time tW. The status of the write operation can be found by reading the Data Polling and Toggle bits (as de- tailed in the READ chapter) or the Ready/Busy output. This Ready/Busy output is driven low from the write of the byte being written until the comple- tion of the internal Write sequence. AI01698B WRITE AAh in Address 5555h WRITE 55h in Address 2AAAh WRITE A0h in Address 5555h SDP is set WRITE AAh in Address 5555h WRITE 55h in Address 2AAAh WRITE A0h in Address 5555h WRITE Data to be Written in any Address SDP ENABLE ALGORITHM Page Write Instruction Page Write Instruction WRITE is enabled SDP Set SDP not Set Write in Memory Write Data + SDP Set after tWC Figure 4. EEPROM SDP Enable Flowcharts 8/30 M39208 |
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