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M29F040-150N3TR Datasheet(PDF) 4 Page - STMicroelectronics |
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M29F040-150N3TR Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 31 page Operation E G W DQ0 - DQ7 Read VIL VIL VIH Data Output Write VIL VIH VIL Data Input Output Disable VIL VIH VIH Hi-Z Standby VIH X X Hi-Z Note: X = VIL or VIH Table 3. Operations Code E G W A0A1A6A9 Other Addresses DQ0 - DQ7 Manufact. Code VIL VIL VIH VIL VIL VIL VID Don’t Care 20h Device Code VIL VIL VIH VIH VIL VIL VID Don’t Care E2h Table 4. Electronic Signature Code E G W A0 A1 A6 A16 A17 A18 Other Addresses DQ0 - DQ7 Protected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 01h Unprotected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 00h Note: SA = Address of block being checked Table 5. Block Protection Status DEVICE OPERATION Signal Descriptions Address Inputs (A0-A18). The address inputs for the memory array are latched during a write opera- tion. The A9 address input is used also for the Electronic Signature read and Block Protect veri- fication. When A9 is raised to VID, either a Read Manufacturer Code, Read Device Code or Verify Block Protection is enabled depending on the com- bination of levels on A0, A1 and A6. When A0, A1 and A6 are Low, the Electronic Signature Manufac- turer code is read, when A0 is High and A1 and A6 are Low, the Device code is read, and when A1 is High and A0 and A6 are low, the Block Protection Status is read for the block addressed by A16, A17, A18. Data Input/Outputs (DQ0-DQ7). The data input is a byte to be programmed or a command written to the C.I. Both are latched when Chip Enable E and Write Enable W are active. The data output is from the memory Array, the Electronic Signature, the Data Polling bit (DQ7), the Toggle Bit (DQ6), the Error bit (DQ5) or the Erase Timer bit (DQ3). Ou- puts are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled. Chip Enable (E). The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. Addresses are then latched on the falling edge of E while data is latched on the rising edge of E. The Chip Enable must be forced to VID during Block Unprotect operations. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. G must be forced to VID level during Block Protect and Block Unprotect operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Addresses are latched on the falling edge of W, and Data Inputs are latched on the rising edge of W. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. 4/31 M29F040 |
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