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M36WV8B10ZA6T Datasheet(PDF) 11 Page - STMicroelectronics |
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M36WV8B10ZA6T Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 92 page 11/92 M36WT864TF, M36WT864BF FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF for the Flash mem- ory and, E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is simultaneous read operations on the Flash and the SRAM which would result in a data bus con- tention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Oper- ation Modes for details). Figure 4. Functional Block Diagram AI06272 Flash Memory 64 Mbit (x16) VSSF RPF WPF E1S E2S GS WS DQ0-DQ15 VDDF VPPF A19-A21 A0-A18 SRAM 8 Mbit (x 16) VSSS VDDS EF GF WF UBS LBS WAITF KF LF VDDQF VSSQF |
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